1. Field of the Invention
The present invention relates generally to design verification, and in particular to verification techniques for debugging systems on chips.
2. Description of the Related Art
Memory dump and scan dump operations are two common operations that may be performed on a fabricated SoC on a development board. These operations are useful during a debugging stage for determining the cause of a SoC malfunction. The memory dump operation may involve reading out all of the memory values of a SoC, and the scan dump operation may involve reading out all of the flip-flop values of a SoC. If a SoC dies unexpectedly or displays some unexpected behavior, the clocks to the SoC may be turned off, and then a scan dump or memory dump operation may be performed.
A SoC may include a series of registers, with each register corresponding to a latch or flip-flop. In a scan dump operation, the contents of each register are shifted to an output scan pin in a concatenated sequence. The sequence of registers in combination with an input scan-in pin and an output scan-out pin may be referred to as a scan chain. In a typical SoC test, a circuit may be stimulated for a specified number of clock cycles and stopped. The contents of each register may then be shifted to an output scan pin. The scan dump operation allows all or a portion of the register or flip-flop values to be observed to help determine the cause of the unexpected behavior. Similarly, a memory dump operation reads out all or a portion of the memory values of the different memories of the SoC. These memory values can be analyzed to help determine the cause of the unexpected behavior.
While the scan dump and memory dump operations are useful for helping in debugging a SoC, before they can be used, these operations are typically verified to make sure they function properly. However, a traditional verification method, such as simulation, is a time-consuming and inefficient method for verifying the scan dump and memory dump operations.